SONY Z3

General	2G Network	GSM 850 / 900 / 1800 / 1900 - D6603, D6643, D6653, D6616
	3G Network	HSDPA 850 / 900 / 1700 / 1900 / 2100 - D6603, D6643, D6653, D6616
	4G Network	LTE 700/800/850/900/1700/1800/1900/2100/2600 (1/2/3/4/5/7/8/13/17/20) - D6603
		LTE 700/800/850/900/1700/1800/1900/2100/2600 (1/2/3/4/5/7/8/17/20) - D6643
		LTE 700 / 850 / 900 / 1800 / 2100 / 2600 - D6653
		LTE 700 / 1700 / 1900 / 2100 - D6616
	SIM	Nano-SIM
	Announced	2014, September
	Status	Available. Released 2014, September

Body	Dimensions	146 x 72 x 7.3 mm (5.75 x 2.83 x 0.29 in)
	Weight	152 g (5.36 oz)
		- IP68 certified - dust proof and water resistant over 1 meter and 30 minutes

Display	Type	IPS LCD capacitive touchscreen, 16M colors
	Size	1080 x 1920 pixels, 5.2 inches (~424 ppi pixel density)
	Multitouch	Yes, up to 10 fingers
	Protection	Shatter proof glass
		- Triluminos display - X-Reality Engine

Sound	Alert types	Vibration; MP3 ringtones
	Loudspeaker	Yes, with stereo speakers
	3.5mm jack	Yes

Memory	Card slot	microSD, up to 128 GB
	Internal	16/32 GB, 3 GB RAM

Data	GPRS	Up to 107 kbps
	EDGE	Up to 296 kbps
	Speed	HSDPA, 42 Mbps; HSUPA, 5.8 Mbps; LTE, Cat4, 50 Mbps UL, 150 Mbps DL
	WLAN	Wi-Fi 802.11 a/b/g/n/ac, dual-band, Wi-Fi Direct, DLNA, Wi-Fi hotspot
	Bluetooth	v4.0, A2DP
	NFC	Yes
	USB	microUSB v2.0 (MHL 3), USB On-the-go, USB Host

Camera	Primary	20.7 MP, 5248 х 3936 pixels, autofocus, LED flash, check quality
	Features	1/2.3'' sensor size, geo-tagging, touch focus, face detection, HDR, panorama
	Video	2160p@30fps, 1080p@60fps, 720p@120fps, HDR, check quality
	Secondary	2.2 MP, 1080p@30fps

Features	OS	Android OS, v4.4.4 (KitKat), planned upgrade to v5.0 (Lollipop)
	Chipset	Qualcomm MSM8974AC Snapdragon 801
	CPU	Quad-core 2.5 GHz Krait 400
	GPU	Adreno 330
	Sensors	Accelerometer, gyro, proximity, compass, barometer
	Messaging	SMS (threaded view), MMS, Email, IM, Push Email
	Browser	HTML5
	Radio	FM radio with RDS
	GPS	Yes, with A-GPS, GLONASS, Beidou
	Java	Yes, via Java MIDP emulator

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General	2G Network	GSM 850 / 900 / 1800 / 1900 - all versions
	3G Network	HSDPA 850 / 900 / 1900 / 2100 - RM-875, RM-877
		HSDPA 850 / 900 / 1700 / 1900 / 2100 - RM-876
	4G Network	LTE 800 / 900 / 1800 / 2100 / 2600 - RM-875
		LTE 700 / 850 / 1700 / 1900 / 2100 - RM-877
	SIM	Micro-SIM
	Announced	2013, July
	Status	Available. Released 2013, July

Body	Dimensions	130.4 x 71.4 x 10.4 mm, 96.9 cc (5.13 x 2.81 x 0.41 in)
	Weight	158 g (5.57 oz)

Display	Type	AMOLED capacitive touchscreen, 16M colors
	Size	768 x 1280 pixels, 4.5 inches (~332 ppi pixel density)
	Multitouch	Yes
	Protection	Corning Gorilla Glass 3
		- PureMotion HD+ ClearBlack display

Sound	Alert types	Vibration; MP3, WAV ringtones
	Loudspeaker	Yes
	3.5mm jack	Yes
		- Dolby Digital Plus - Dolby headphone enhancement

Memory	Card slot	No
	Internal	32 GB, 2 GB RAM / 64 GB (Telefonica exclusive)

Data	GPRS	Yes
	EDGE	Up to 236.8 kbps
	Speed	HSDPA, 42.2 Mbps; HSUPA, 5.76 Mbps; LTE, Cat3, 50 Mbps UL, 100 Mbps DL
	WLAN	Wi-Fi 802.11 a/b/g/n, dual-band, DLNA, Wi-Fi hotspot
	Bluetooth	v3.0, A2DP/ v4.0, LE after WP8 Black update
	NFC	Yes
	USB	microUSB v2.0

Camera	Primary	41 MP (38 MP effective, 7152 x 5368 pixels), Carl Zeiss optics, optical image stabilization, auto/manual focus, Xenon & LED flash, check quality
	Features	1/1.5'' sensor size, 1.12 µm pixel size, PureView technology, geo-tagging, face detection, dual capture, panorama
	Video	1080p@30fps, optical stabilization, 4x lossless digital zoom, check quality
	Secondary	1.2 MP, 720p@30fps

Features	OS	Microsoft Windows Phone 8, upgradeable to WP8, upgradeable to v8.1
	Chipset	Qualcomm MSM8960 Snapdragon
	CPU	Dual-core 1.5 GHz Krait
	GPU	Adreno 225
	Sensors	Accelerometer, gyro, proximity, compass, barometer
	Messaging	SMS (threaded view), MMS, Email, Push Email, IM
	Browser	HTML5
	Radio	Stereo FM radio with RDS
	GPS	Yes, with A-GPS, GLONASS
	Java	No

The Von Neumann architecture, also known as the Von Neumann model and Princeton architecture, is a computer architecture based on that described in 1945 by the mathematician and physicist John von Neumann and others in the First Draft of a Report on the EDVAC.^[1] This describes a design architecture for an electronic digital computer with parts consisting of a processing unit containing an arithmetic logic unit and processor registers, a control unit containing an instruction register and program counter, a memory to store both data and instructions, external mass storage, and input and output mechanisms.^[1][2] The meaning has evolved to be any stored-program computer in which an instruction fetch and a data operation cannot occur at the same time because they share a common bus. This is referred to as the Von Neumann bottleneck and often limits the performance of the system.